1. Field of the Invention
The present invention relates to a test circuit for a semiconductor memory device and a method for performing a test.
Particularly, the present invention relates to a test circuit for screening out failures such as a microshort of a gate oxide film of transistor, a p/n junction, a dielectric film of memory cell capacitor, between storage nodes of memory cell capacitors, between a storage node and a bit line, and between a storage node and a word line in a wafer-level burn-in test and a test equivalent thereto and to a method for screening out these failures in such tests.
More particularly, the present invention relates to a wafer-level burn-in test circuit, an outgoing test circuit and so on for realizing a checker pattern on a semiconductor memory device as a test pattern and to a method for performing such tests.
2. Discussion of Background
Conventionally, a burn-in test, of which purpose is to screen out by tangibly drawing out potential failures of a dynamic random access memory (DRAM), was performed in a step of outgoing test. In recent years, the situation was changed and the main stream is that a step of testing a DRAM is performed by a wafer-level burn-in (WLBI) in a wafer test step. By introducing the WLBI test, it is possible to screen potential failures in a DRAM out at an initial stage in steps for testing, whereby a yield in the step of outgoing test is stabilized and a cost for testing can resultantly be compressed.
In a conventional WLBI, a method of simultaneously activating word lines was proposed. According to the method, a principal objective was to boost a voltage applied to gate oxide films of memory cell transistors. FIG. 7 shows an example of a circuit structure according to a conventional WLBI circuit of simultaneously activating word lines, wherein references WL&lt;i&gt; and WL&lt;j&gt; respectively designate any one of word lines arranged in even order and any one of word lines arranged in odd order; references WD&lt;i&gt; and WD&lt;j&gt; designate word line driving circuits of working as an inverter, which circuits respectively correspond to the word lines WL&lt;i&gt;, WL&lt;j&gt;. . . ; and references ZWL&lt;i&gt; and ZWL&lt;j&gt; designate row decoding signals respectively corresponding to the word line driving circuits WD&lt;i&gt; and WD&lt;j&gt;.
In FIG. 8, references Xa, Xb, Xc designate row address signals; reference RD&lt;i&gt; designates one of row decoding circuits; reference WD&lt;i&gt; designates one of word line driving circuits corresponding to the row decoding circuit; reference ZWL&lt;i&gt; designates one of row decoding signals corresponding thereto; and reference WL&lt;i&gt; designates one of word lines corresponding thereto. In a usually used operation not in WLBI, for example, shown in FIG. 8, a row address Xa, Xb, Xc . . . input from an outside of chip is decoded by a row decoding circuit and a word line WL&lt;i&gt;is activated to conduct read operation, write operation and so on.
In FIG. 7, the row decoding signals ZWL&lt;i&gt; and ZWL&lt;j&gt;, which respectively become a level H under a non-selected state to respectively render word lines WL&lt;i&gt; and WL&lt;j&gt; a level L and become a level L under a selected state to respectively render the word lines WL&lt;i&gt; and WL&lt;j&gt; a level H, wherein the level H means a Vpp level sufficiently enough to write data of H to memory cells. The reference Vpp has a higher level than Vcc and is generated by a Vpp generating circuit usually provided in an inside of a chip. For example, in a case that Vcc is 3.3 V, Vpp is about 3.6 through 4.0 V.
In this method, a high voltage supplied from a pad for supplying a stress voltage (VWL) to word lines is applied to word lines through transistors such as Q4 and Q5, which transistors constitute a circuit for driving word lines. Specifically, when the WLBI test is performed, all of the word lines can be simultaneously boosted by applying a voltage of a high (H) level to a pad for controlling burn-in (BICNTL) and applying a predetermined high voltage to the pad (VWL), for example, as disclosed in U.S. Pat. No. 5,590,079.
However, in the WLBI according to the above-mentioned conventional method of simultaneously activating word lines, a voltage stress could be applied to only gate oxide films of memory cell transistors connected to thus activated word lines.
Also, there was a problem that an effective screening could not be performed because of insufficient voltage boosting with respect to memory cells.
Such insufficient voltage boosting was caused because one particular word line could be selected once in every thousands of cycles, for example, 1024 for 4M DRAM, 2048 or 4096 for 16M DRAM, and 4096 or 8192 for 64M DRAM. For example, on the assumption of a 50% word line duty ratio and "1/0" alternating cell data, a transfer gate of a particular memory cell was exposed to the maximum stress for 1/16K or 1/32K of the total burn-in period for the 64M DRAM case. Further, FIG. 3b schematically shows a structure of memory cells 6, wherein numerical reference 61 designates a gate oxide film; numerical reference 62 designates a p/n junction; numerical reference 63 designates a storage node; and numerical reference 64 designates a capacitor dielectric.
In order to conduct an effective screening, it is necessary to check possible leakage not only at gate oxide films 61 but also that at p/n junctions 62, storage nodes 63, capacitor dielectric films 64, or the like. For this, it is proposed that all transfer gates, namely gate oxide films 61, are simultaneously turned on and storage node potential (namely, bit line level) and capacitor plate bias are externally controlled, whereby a desired stress can be applied to the capacitor, particularly to its dielectric films or the junctions for the desired period without a stress relaxation.
In order to realize such condition, it is important to develop a technology of simultaneously probing as many chips on a wafer as possible. The WLBI time per chip is reduced as the number of chips simultaneously probed increases.
Although a wafer prober for testing a wafer shown in FIGS. 9 through 11 is not exclusively used for a WLBI test, it can be used for testing a semiconductor memory device by WLBI.
Such a wafer prober is disclosed, for example, in the journal "Nikkei Micro Device Vol. 1998/8", pages 61 through 65. Structure and function of a wafer prober will be described with reference to FIGS. 9 through 11.
In FIGS. 9 through 11, numerical reference 10 designates a wafer; numerical reference 11 designates a wafer prober; numerical reference 12 designates a test head; numerical reference 13 designates a probe card; numerical reference 14 designates a probe pin; numerical reference 15 designates a wafer chuck; numerical reference 16 designates a card holder; numerical reference 20 designates a test station; numerical reference 21 designates a test-cable; and numerical reference 22 designates a tester I/F or GP-1B.
FIG. 9 shows a system for wafer test; FIG. 10 shows a wafer chuck 15 and peripheral portions thereto in a wafer prober 11; and FIG. 11 schematically shows a cross-section of a test head 12, the wafer chuck 15 of the wafer prober 11, and peripheral portions thereto.
Generally, processes of manufacturing a semiconductor device includes a first process of forming a circuit pattern and a second process of cutting a wafer, bonding, and packaging. In the end of the first process, a wafer testing step is performed to test a test chip such as a device in a semiconductor wafer 10 to be loaded for judging whether or not the test chip is acceptable.
As shown in FIG. 9, a system for wafer test comprises a test station 20 for performing the test of the test chip, a probe card 13 to be in contact with pads of the test chip, and a wafer prober 11 for transferring a wafer 10 and positioning probe pins 14. Above a head plate, a test head 12 of the test station 20 is located. Further, the probe card 13 is attached to the head plate. The test station 20 sends and receives a test signal to and from the test chip on the wafer 10 through contacts with the probe pins 14 of the probe card 13, whereby the test is performed.
In order to tangibly draw out the above-mentioned possible leakages, it is necessary to simultaneously probe as many chips on the wafer as possible and to provide additional probe pins 14 for simultaneously activating gate oxide films and externally controlling the storage node potential and the capacitor plate bias.
However, in accordance with the recent increment of a DRAM capacity, it became difficult that these increased and/or additional probe pins 14 were provided in a probe card 13. Therefore, if a DRAM is originally designed aiming a WLBI application, it is quite easy to implement a mechanism where almost all the circuits in the DRAM are activated including column circuits while using an embedded address counter and minimizing the number of WLBI pads, as disclosed in IEDM '93 p. 639-642, International Electron Devices Meeting, Technical Digest.
However, the usage of such an embedded address counter still makes the WLBI test complicated.
Incidentally, in order to test a microshort between word lines, it was proposed in U.S. Pat. No. 5,265,057 that adjacent memory cells in a DRAM respectively had a state of high (H) or a state of low (L) so as to form a checker pattern. Namely, viewing all of the memory cells when memory cells in the state H are shaded and memory cells in the state L are blanked, the DRAM schematically exhibit a checker pattern However, the checker pattern was conventionally used to check only the microshort between word lines because of the above-mentioned restriction in probe cards and the above-mentioned structure of the test circuit. Thus, it could not be used to screen out the other potential failures.
Further, in a conventional WLBI circuit of a semiconductor memory device, it was impossible to perform a test equivalent to the WLBI test after packaging the device because the device was designed such that terminal pins or pads necessary for the test were covered with the package shell, since it is not preferable that users can access these and in consideration of a small packaging requiring the least outer terminals.